The present invention relates generally to integrated circuits (ICs), and more particularly, to functional testing of a Sigma-Delta modulator circuit.
Improvements in semiconductor technology have led to an increase in the complexity of integrated circuit design. Further, noise such as quantization noise, thermal noise, and the like are introduced into complex ICs. A sigma-delta modulator (SDM) reduces quantization and thermal noise in digital output signals and oscillating signals of complex circuits such as analog-to-digital converters (ADCs) and phase-locked loop (PLLs), respectively. Thus, the SDM has become an essential component of ADCs and PLLs.
The operation of PLLs is well known. A PLL includes a phase-frequency detector, a voltage-controlled oscillator (VCO), a divider, a loop filter, and an SDM. The SDM receives a PLL input signal as the SDM input signal and provides an SDM output signal. The divider is connected to the SDM and receives the SDM output signal. The PLL generates the oscillating signal based on the PLL input signal and the SDM output signal at a predetermined frequency, which is in a predetermined frequency range. The PLL may malfunction when the oscillating signal generated by the PLL is at a frequency that is not equal to the predetermined frequency. Generally, when the SDM functions incorrectly, the oscillating signal generated will not be at the correct frequency. Hence, to ensure the correct operation of the PLL, the accuracy of the SDM must be checked, which can be done by a test circuit that performs a functional test on the SDM.
One way to test the SDM is to connect a test circuit to the PLL (which includes the SDM). The test circuit may be an external oscilloscope or an internal control circuit. The test circuit receives the oscillating signal and checks whether the frequency of the oscillating signal is within the predetermined frequency range. The test circuit determines that the PLL is not functioning correctly when the frequency of the oscillating signal is outside of the predetermined frequency range. However, this technique fails to identify the component of the PLL causing the fault in the oscillating signal. Further, the test circuit tests the VCO and the loop filter but fails to test the SDM even though the SDM usually contributes to inaccuracy in the frequency of the oscillating signal.
One technique to overcome the aforementioned problem is the use of a BIST circuit, which includes a digital-to-analog converter (DAC) and an averaging circuit. The DAC is connected to the SDM to receive the SDM output signal, and generate an analog SDM output signal. The averaging circuit receives the analog SDM output signal and generates an average value of the analog SDM output signal. The BIST circuit compares the average value of the analog SDM output signal with the SDM input signal and generates an SDM test signal. The SDM test signal indicates that the SDM is functioning correctly when the average value of the analog SDM output signal matches the SDM input signal. However, when the rate at which the DAC receives the SDM output signal is less than that at which the SDM output signal is generated, the BIST circuit will fail to accurately receive the SDM output signal, which is undesirable. Further, when the DAC receives the SDM output signal at a rate that is equal to that at which the SDM output signal is generated, the power consumption of the DAC is increased. The DAC and the averaging circuit also introduce a delay into the generation of the SDM test signal and increase the complexity and area of the BIST circuit.
It would be advantageous to have a BIST circuit to test an SDM such that the BIST circuit accurately reads an SDM output signal without causing a significant increase in the complexity and the power consumption of the BIST circuit.